(1) Field of the Invention
The present invention relates generally to semiconductor manufacturing, and more particularly to a method for preventing gate oxide damage during post poly definition implantation.
(2) Description of the Related Art
Reliability of gate oxides in integrated circuits (IC) is of the utmost importance in providing high performance IC chips. The main performance criteria in digital CMOS ICs are, among others, speed and packing density. As is well known in the field, scaling down, that is, reducing device size has been the chief vehicle for achieving increased packing density. Scaling down device size in turn, means using smaller channel lengths and widths. To increase the speed, the saturation drain current (I.sub.dsat) must be increased. It is known that a decrease in either the channel length or the gate oxide thickness (t.sub.ox) will lead to an increase in I.sub.dsat. Furthermore, I.sub.dsat will increase more rapidly if gate oxide is made thinner at the same time. Thus, this provides even a greater incentive for growing gate oxide as thin as possible as gate channel lengths are decreased further in the drive for higher density ICs.
Gate oxide thickness has grown smaller with each generation of MOS ICs. It is believed that the current trend will lead to gate oxide thicknesses below 5 nanometers (nm) as the MOSFET technology is scaled below 0.5 micrometers (.mu.m). It is also believed that unless the power supply voltage is also reduced--even lower than the 3.3V in some 0.5 .mu.m CMOS technologies of today--there will be severe reliability problems in oxide films thinner than 10 nm. While the benefits of using thin oxides are well known in the field, such oxides must exhibit adequate reliability characteristics under normal circuit operating conditions. An additional contributor to the reliability concerns is the damage caused to thin gate oxides when a metal conductor such as the polysilicon gate over gate oxide is locally charged. Such local charging can occur when a semiconductor wafer is subjected to any number of semiconductor processes involving, for example, plasma etching or ion implantation.
Thin oxide films undergo catastrophic failures when stressed by high electric fields. High electric fields can result when surface charging occurs on a semiconductor wafer. How isolated conductor regions on a wafer surface can be charged up by plasma is described elsewhere (See S. Wolf and R. N. Tauber, "Silicon Processing for the VLSI Era," vol. 3, Lattice Press, Sunset Beach, Calif., 1990, pp. 504-505.) and as they are not significant to the invention, they are not described in detail here in order not to unnecessarily obscure the present invention. It is sufficient to note that if the plasma is non-uniform, the ensuing ion and electron currents on the surface of the wafer are also non-uniform. If a region of the surface is an insulator, the non-uniform current flows can set up a charge locally. Following Wolf above, if, specifically, an island of conductor material is sitting on an oxide, and this island is elsewhere not connected to a substrate (10) as shown in FIG. 1 (e.g., a poly line (35) that serves as a gate), the locally non-uniform ion and electron currents can charge the conductor. The surface area of such a conductor exposed to impingement by the charged plasma is known as the antenna surface. It is to be noted in FIG. 1 that aluminum lines (45) are being formed by plasma etch (50). Metal layer (45) is separated from the poly interconnect layer (35) below by a chemical vapor deposited (CVD) oxide layer, or interlevel dielectric. The metal lines are then patterned by photoresist mask (40). Hence, aluminum line (45) becomes the antenna. Since the antenna can span both the thick oxide (field regions, 20) and thin oxide (gate regions, 30) as shown in FIG. 1, the antenna/thin oxide area-ratio can exceed unity. The charging will therefore result in an increased voltage across the thin oxide. This charge build up will continue until the non-uniform currents will balance out, or the oxide begins to conduct. If the oxide begins to conduct, for example, by the well-known Fowler-Nordheim tunneling phenomenon, charge passage through the oxide may cause damage that can eventually lead to oxide breakdown failure.
Antenna structures are especially suited for testing of gate oxide for damage caused by Fowler-Nordheim tunneling due to charge build up on the poly gate during exposure to plasma ions. Using such structures as test structures, it can be shown that the extent of damage is dependent upon the amount of surface area or the edge area of the poly gate that is exposed to the plasma. Thus, a masking method is proposed in this invention whereby the exposed surface area as well as the edge area of the conductor attached to the poly gate on the field oxide can be made very small so as to prevent gate oxide damage. In other words, the effective antenna ratio, namely, the ratio of the plasma exposed area of the antenna region over field oxide to the area of the gate over the gate oxide, can be made to approach zero by judicious masking. It will be shown in the preferred embodiments of this invention that with small effective antenna ratios, oxide damage can be prevented during exposure of wafer to ions and electron currents.
In prior art, masking methods have been devised in fabricating IC devices, but mainly for the purposes of defining dimensions associated with the gate, gate oxide, and the channel length between the source and drain of the device. In U.S. Pat. No. 5,348,897, for example, Yen proposes using overlapping masks so that one could achieve a smaller device area and hence higher packing density. However, it is not clear how this approach can alleviate oxide damage during ion implantation, especially when heavy doping is performed. What is needed therefore is a masking method designed to reduce the effective antenna ratio to zero, and hence prevent oxide damage during exposure to plasma ions as well as ion implantation.